Heterogeneous Integration Process Incorporating Layer Transfer in Epitaxy Level Packaging

ABSTRACT

Methods and structures for heterogeneous integration of diverse material systems and device technologies onto a single substrate incorporate layer transfer techniques into an epitaxy level packaging process. A planar substrate surface of multiple epitaxial areas of different materials can be heterogeneously integrated with a substrate material. Complex assembly and lattice engineering is significantly reduced. Microsystems of different circuits made from different materials can be built from a single wafer Fab line employing the claimed processes.

RELATED APPLICATION DATA

The present application claims priority to and is a divisional of Ser.No. 13/724,701, filed Dec. 21, 2012, which latter application claims thebenefit under 35 U.S.C. §119(e) of the priority date of ProvisionalApplication Ser. No. 61/580,044, filed Dec. 23, 2011, both of which arehereby incorporated by reference.

FIELD OF THE INVENTION

The present invention relates to structures and methods of heterogeneousintegration of diverse material systems and device technologies onto asingle substrate in the fields of semiconductors and relatedheterogeneous integration among microelectronics, optoelectronics,electromechanics, thermoelectrics, photovoltaics, thermo-photovoltaics,electrochemical, photo-electrochemical, piezoelectrics, superconductors,etc.

BACKGROUND

The following documents are incorporated by reference herein:

1. M. Bruel, “A new silicon on insulator material technology”, Electron.Lett. 31, 1201-1202 (1995).

2. U.S. Pat. No. 5,374,564 M. Bruel

3. M. Wanlass et al., “Monolithic, Ultra-Thin GaInP/GaAs/GaInAsTandemSolar Cells,” NREL/PR-520-39852, Presented at the 2006 IEEE 4th WorldConference on Photovoltaic Energy Conversion (WCPEC-4) held May 7-12,2006 in Waikoloa, Hi.

4. F. J. Kub et al., “Ultra-Thin Silicon Complaint Layers for InfraredMaterials,” Naval Research Laboratory/OMB 0704-0188, 1998.

5. M. S. Goorsky et al., “Engineered Layer Transfer Substrates forHeterogeneous Integration of III-V Compound Semiconductors,” 2008 TheInternational Conference on Compound Semiconductor ManufacturingTechnology.

6. R. Brendel, “Crystalline thin-film silicon solar cells fromlayer-transfer processes: a review,” Proc. 10th Workshop on CrystallineSilicon Solar Cell Materials and Processes, Aug. 13-16, 2000, CopperMountain, USA.

7. U.S. Pat. No. 7,855,101 B. K. Furman et al.

8. M. M. A. J. Voncken et al., “Etching AlAs with HF for EpitaxialLift-Off Applications,” Journal of the Electrochemical Society, 151, no5 (2004): G347-G352.

9. N. M. Jokerst et al., “The Heterogeneous Integration of OpticalInterconnections Into Integrated Microsystems,” IEEE JOURNAL OF SELECTEDTOPICS IN QUANTUM ELECTRONICS, 9, no. 2, MARCH/APRIL 2003.

10. X. Y. Lee et al., “Thin Film GaAs Solar Cells on Glass Substrates byEpitaxial Liftoff,” National renewable energy laboratory and sandianational laboratories photovoltaics program review meeting. AIPConference Proceedings, 394, (1997): 719-727.

11. M. J. Archer et al., “Materials Processes for Ultrahigh EfficiencyLattice Mismatched Multijunction Solar Cells,” SPIE Optics+Photonics(2007): 6649-14.

12. U.S. Pat. No. 7,935,612 S. Bedell et al.

13. U.S. Pat. No. 7,905,197 E. T-S. Pan

14. U.S. Pat. No. 8,193,078 E. T-S. Pan

15. U. Gosele et al., “Fundamental Issues in Wafer Bonding,” JOURNAL OFVACUUM SCIENCE AND TECHNOLOGY A, 17(4), July/August 1999.

Prior art layer transfer methods typically separate grown epitaxylayer(s) or finished device structure from a parent wafer substrate to adaughter substrate. The different types of prior art processes typicallypracticed as follows:

1) Commonly known as Ion Cut or Smart Cut—cleave fine monocrystallinelayers by inducing, through ion implantation to create a mechanicallyweak zone below the surface of the donor wafer. The implanted wafer isthen bonded to a handle wafer and the obtained pair is subjected tothermal annealing to produce voids and extended internal surfaces interms of pressurized microcracks parallel to the bonding interface. Thisleads to the splitting and transfer of a thin monocrystalline layer witha thickness roughly equivalent to the implantation depth (see references#1, #2 above).

2) Deposit a backside contact and back surface reflector atop aninverted tandem structure which is grown on an etch stop layer over afirst substrate. Mount the inverted tandem structure upside down on asecond substrate. Remove the etch stop layer and thus the firstsubstrate. Complete frontside processing of the tandem structure on thesecond substrate (see reference #3).

3) Deposit some layers on a first substrate, and other layers on asecond substrate. Polish and bond the two-layered substrates byannealing. Detach the second substrate by a hydrogen implantation,leaving the desired layer combination on the first substrate (seereferences #4, #5).

4) Prepare a surface layer (surface conditioning) on a siliconsubstrate. Grow a device layer on the surface treated layer. Attach acarrier to the device layer. Remove the surface layer and the siliconsubstrate (see reference #6).

5) Build a semiconductor device layer on a first substrate. Provide aset of first functional elements to connect in the semiconductor devicelayer. Attach a carrier substrate on top of the first functionalelements. Remove the first substrate to expose the bottom side of thesemiconductor device layer producing a first intermediate structure.Build a set of second functional elements on a foundation substrate toproduce a second intermediate structure. Bond the first and the secondintermediate structures to form a third intermediate structure. Removethe carrier substrate. Provide input output means on the exposed surfaceof the first functional elements to form the integrated device structure(see reference #7).

6) An epitaxial lift-off process allows the separation of a thin layerof compound semiconductor material from a substrate bystrain-accelerated selective etching of an intermediate or sacrificiallayer. Other means of removing the sacrificial layer in ELO includelaser-assisted lift-off, ion bombardment (see reference #8).

7) Fabricate devices on an etch stop layer (epitaxial surface) grown ona substrate. Mesa etch to etch stop layer and pattern separate devices.Remove the substrate using selective wet etching. Bond the device onto ahost substrate using a transfer diaphragm (see reference #9).

8) Wax the top of a device. Lift-off in a selective chemical etch of asacrificial layer and remove the substrate. Attach the lift-off deviceto a glass substrate. Remove wax in chemical removal step (see reference#10).

9) Implant a device template substrate. Activate and clean the surfaceof the device template substrate and the handle substrate. Initiate abond at room temperature. Apply uniform pressure and heat to the stackedwafers to strengthen the bond and initiate exfoliation (see reference#11).

10) Form an upper silicon (Si) layer over a boron-doped SiGe layer.Hydrogenate the boron-doped SiGe layer by hydrogen plasma without ionimplantation. Bond the upper Si layer to an alternate substrate andpropagate a fracture at an interface between the boron-doped SiGe layerand the bulk silicon substrate (see reference #12).

Other improved processes are shown in references #13 and #14 above tothe instant inventor. There is still a need for further improvements inthis field.

SUMMARY OF THE INVENTION

An object of the present invention, therefore, is to overcome theaforementioned limitations of the prior art. It will be understood fromthe Detailed Description that the inventions can be implemented in amultitude of different embodiments. Furthermore, it will be readilyappreciated by skilled artisans that such different embodiments willlikely include only one or more of the aforementioned objects of thepresent inventions. Thus, the absence of one or more of suchcharacteristics in any particular embodiment should not be construed aslimiting the scope of the present inventions.

The present disclosure describes a plurality of embodiments applyinglayer transfer (e.g. ion-induced exfoliation) techniques to anepitaxy-level packaging (ELP) method (see reference #13, #14) ofepitaxial layer growth from a crystalline parent substrate intothrough-substrate vias to form epitaxial islands (or pillars) in anassembly daughter substrate to provide a wafer substrate as a commonsubstrate platform for further wafer fabrication to achieveheterogeneous integration. There are two insertion points to incorporatelayer transfer into the ELP process—before and after epitaxial islandgrowth.

From the perspectives of material, processing, and assembly, ELP makesefficient use of compound semiconductor material by growingislands/pillars rather than wafers, and has the ability to integrateseveral different materials on the same wafer platform (e.g. silicon)using existing wafer fabrication processes. Wafer level heterogeneousintegration is readily achievable by selective masking and demasking ofELP islands and Si area by either fabricating each microsystemsequentially or fabricating multiple microsystems by inserting modularsteps of one microsystem into the flow of another microsystem atappropriate steps while preserving the electrical integrity of allmicrosystems.

Aspects of the invention extend the ELP method into semiconductor waferfabrication process flow for heterogeneous integration of one or morecompound semiconductor (CS) materials in the form of multiple ELPhomoepitaxy areas that are on the same planar surface as the surface orsub-surface of assembly substrate (e.g. made of silicon with an oxidizedlayer). Devices and ICs can be built from a single wafer fabricationline with interconnects among a diversity of devices made out ofdifferent materials.

A first aspect of the invention concerns methods of forming epitaxialstructures, in which an exfoliation takes place in a crystallinesubstrate prior to using an assembly substrate to create an epitaxialpattern. A handling substrate is employed to assist in separating arecrystallized exfoliation layer from the crystalline substrate.

A second aspect of the invention concerns methods of forming epitaxialstructures, in which an exfoliation takes place in an assembly substrateafter an epitaxial layer/pattern has been formed. A handling substrateis employed to assist in separating a recrystallized exfoliation layerfrom the assembly substrate. Additional processing can be performed insome applications to split/divide the assembly substrate into twodistinct halves which can be further processed.

A third aspect of the invention concerns methods of forming epitaxialstructures, in which an exfoliation takes place during a time that anepitaxial layer/pattern is being formed in an assembly substrate.

Additional aspects of the invention are directed to the resultingstructures from the aforementioned processes, including an epitaxialstructure formed in an assembly substrate that includes an ion implantedexfoliation layer. Other aspects concern assembly substrates whichinclude different types of epitaxial material in different regions, thusallowing heterogeneous integration of different microsystems.

DESCRIPTION OF THE DRAWINGS

FIG. 1A illustrates a preferred embodiment of a method of applying layertransfer before ELP epitaxial island/pillar growth;

FIG. 1B illustrates a preferred embodiment of a method of applying layertransfer after ELP epitaxial island/pillar growth;

FIG. 1C illustrates an approach of a selective ion implant to create auniform exfoliation plane at the same depth across different materials;

FIG. 1D illustrates another approach of blanket ion implant withcompensating thin film to create a uniform exfoliation plane at the samedepth across different materials;

FIG. 1E illustrates yet another approach of blanket ion implant withcompensating etching to create a uniform exfoliation plane at the samedepth across different materials;

FIG. 1F illustrates a preferred embodiment of a method of applying layertransfer with ion implantation before ELP epitaxial island growth andwith exfoliation after ELP epitaxial island growth;

FIG. 2A illustrates a preferred embodiment of a process flow for makingan ELP wafer substrate incorporating layer transfer;

FIG. 2B illustrates a preferred embodiment of a process flow using anELP wafer substrate for heterogeneous integration incorporating layertransfer.

DETAILED DESCRIPTION

As discussed in the background of this invention, there are a number ofmethods to achieve layer transfer. All layer transfer methods involve asacrificial layer or a separation layer. Ion-induced exfoliation is oneof the most widely adapted layer transfer method in the industry and canbe applied to a variety of crystalline materials. For illustrationpurpose in the FIGS. 1A-F and 2A-B, ion-induced exfoliation is used asthe layer transfer technique for ELP wafer formation. Other applicablelayer transfer techniques may also be used in place of ion-inducedexfoliation.

In FIG. 1A, Inset 1 shows that an ion beam flux 110 irradiates (i.e.causes ion implantation) unto a preferably bare crystalline substrate120 (although it will be understood that other materials that do notinterfere with the process could be on the surface). The ion beam flux110 is generally defined by its ion species, dose (ions/area), andenergy. For ion-induced exfoliation, substrate temperature and ion beamincident angle during ion implantation also influence the degree ofexfoliation.

Ion implantation preferably creates an interfacial plane 122 ofion-induced damages to the crystalline structure at a certain targetdepth below the surface of crystalline substrate 120 (Inset 2). Thevolume between the interfacial plane 122 and the surface of thecrystalline substrate defines a thin layer 125 to be exfoliated orseparated from the crystalline substrate.

A separate handling substrate 130 is preferably used to bond to the ionimplanted surface of the crystalline substrate 120 (Insets 3) beforelayer transfer (exfoliation) by annealing (Inset 4). In someembodiments, it may be possible to grow handling substrate directly on(at least portions of) substrate 120. During annealing, implanted ionsare released from the trapping sites and accumulate on platelets formedduring implantation. Due to an increase of inner pressure, plateletsgrow and overlap, eventually leading to the formation of microcavitiesfollowing a path parallel to the substrate surface. Gas-containingmicrocavities gradually grow and an interaction between neighboringmicrocavities occur and result in the propagation of a crack along thecavity plane. An optimal range of ion implantation temperature can beused for controlled formation of platelets.

In preparation for layer transfer, the surfaces of layer 125 andhandling substrate 130 should preferably be chemically conditioned(reference #15) and cleaned before bonding for exfoliation. Bonding oradhesion can be initiated by bringing the two surfaces in contact witheach other through applying localized pressure. Actual bonding isachieved by van der Waals interactions. Control of post-implantannealing temperature at a lower temperature (typically less than 300°C.) and conditions is important for layer separation from theinterfacial plane 122, especially for layer transfer between dissimilarmaterials with very different thermal expansion coefficients. Thesequence of actions preferably leads to layer separation in directionparallel to the bonded surface and completes the transfer of layer 125from the crystalline substrate 120 to the handling substrate 130 (Inset5). Other techniques known in the art or later developed and which areconsistent with the present teachings can be employed to effectuateexfoliation.

The transferred thin layer 125 may then be polished for planarizationand preferably annealed for repairing implant damages,recrystallization, and/or dopant activation to prepare a crystallinetemplate 129. An assembly substrate 140 (preferably a silicon basedmaterial but including compositions such as SiC, SiO₂, Si₃N₄, andsimilar oxide and non-oxide ceramics or glasses) having desired etchingor patterning profile including through-substrate vias 145 is pressedagainst (preferably without atomic bonding to) thin layer 125 which isbonded to a handling substrate 130 in an epitaxial growth apparatus(Inset 6). As epitaxial layer grows from the surface of crystallinelayer 125 at the bottom of through-substrate vias 145 within theassembly substrate 140, grown epitaxial layer eventually fills upthrough-substrate vias to form epitaxial islands/pillars 150 (Inset 7).After epitaxial layer growth, handling substrate 130 may be debondedfrom layer 125. Layer 125 may also be removed or further thinned down bystandard planarization techniques such as Chemical MechanicalPlanarization (CMP) to complete the ELP substrate 160 (Inset 8).

FIG. 1B describes an embodiment of making ELP substrate 160 (Inset 15)having a layer transfer after epitaxial layer growth. Crystallinesubstrate 120 and the assembly substrate 140 having an epitaxialpattern, including a desired etch profile and through-substrate vias 145(Inset 9) are pressed against each other preferably without atomicbonding (Inset 10) for epitaxial island 150 growth filling upthrough-substrate vias (Inset 11). An ion beam flux 110 irradiates (i.e.ion implantation) unto the assembly substrate 140 and epitaxial islands150 for ion-induced exfoliation (Inset 12). Basically an exfoliationdepth is dependent upon the mass and energy of the ion and the atomicdensity of the target material. In case of ion-induced exfoliation of aheterogeneous layer consisting of two or more different materials,creating a uniform exfoliation plane at the same depth across differentmaterials has challenges but can be achieved by two approaches.

One approach—shown in FIG. 1C—is to perform selective ion implantationwhere different materials (i.e. epitaxial islands and assemblysubstrate) receive ion implantation of different conditions at selectiveareas through multiple masking and demasking steps. Thus, two separateimplants could be performed to achieve a reasonably consistent targetdemarcation depth/size for the exfoliation layer.

Another approach—as shown in FIGS. 1D/1E—compensates uniformity ofexfoliation depth by depositing a thin film over or etching off for eachmaterial such that the same ion implantation conditions can bepreferably applied over the entire assembly substrate and the epitaxialislands at the same time (i.e., blanket ion implantation). It will beunderstood that the relative thicknesses shown in FIGS. 1D/1E of thelayers, masks, etc. are only intended to be illustrative and are notdrawn to scale. They will vary in accordance with a density, compositionof the materials used for the assembly substrate and the epitaxiallayer. Moreover the use of the thin film is shown to be used to mask theassembly substrate, but in any final implementation this may vary inaccordance with the particular assembly substrate and epitaxialmaterials used.

After ion implantation is achieved and a uniform exfoliation plane 122is formed, a handling substrate 130 is preferably bonded to thetransferring layer 127 above the exfoliation plane 122 (Insets 13, 14).Ion-induced exfoliation is accomplished by annealing thus preferablyleaving two separate halves or composites (Inset 15). The firstcomposite is the ELP substrate 160 consisting of the transferred layer127 that is planarized, annealed for repairing implant damages, andbonded to handling substrate 130. The second composite consists ofremaining layer 128 attached to the crystalline substrate 120. In caseof heterogeneous epitaxial islands/pillars, crystalline substrate 120may consist of multiple crystalline substrate pieces. The secondcomposite may be ion implanted (Inset 16) for another ion-inducedexfoliation (repeating the process in Insets 13-16 in one or more timesto produce multiple ELP substrates).

FIG. 1F describes yet another embodiment of an in-situ epitaxialisland/pillar growth and layer separation. The crystalline substrate 120is implanted with an ion flux 110 (Inset 20) preferably creating a thinlayer 125 to be exfoliated or separated from the crystalline substrate120 at the interfacial plane 122 (Inset 21). The assembly substrate 140with through substrate vias 145 (Inset 22) is brought into contact(preferably with no atomic bonding) onto the surface of the thin layer125 un-separated from its crystalline substrate 120 (Inset 23) and beput into an epitaxial layer growth apparatus. By choosing an ion species(for example, H, He or N) and optimizing among implant conditions andprocessing temperatures at various steps (i.e. recrystallization,epitaxial layer growth, and exfoliation), an in-situ process (within theepitaxial layer growth apparatus) can be achieved such thatrecrystallization of layer 125 can be performed first at a temperaturepreferably lower than the peak temperatures of epitaxial growth andexfoliation.

Then an epitaxial layer growth filling out the through substrate vias145 to form epitaxial islands or pillars 150 can be carried outpreferably at a temperature-duration profile that does not initiateexfoliation (Inset 24). Exfoliation can be performed preferably at theend of epitaxial island growth in-situ or ex-situ to remove crystallinesubstrate 120 (Inset 25).

Further processing to remove thin layer 125 may be performed to form theELP substrate 160 (Inset 26). Exfoliation of the thin layer 125 from thecrystalline substrate 120 and removal of the thin layer 125 may also beperformed during or after the formation of microsystems (not shown inFIG. 1F). The thin layer 125 may also be formed without ion implantationand be removed by preferential chemical etching.

Furthermore, in this embodiment exfoliation of crystalline substrate canalso occur before or contemporaneous with epitaxial growth. Because thecrystalline substrate 120 is physically confined in a holding apparatus(not shown) the separated exfoliated top layer from crystallinesubstrate stays in place for subsequent epitaxial growth. As epitaxiallayer growth is completed, the ELP wafer is completed with epitaxialislands or pillars and separated from the crystalline substrate in onestep. The ELP wafer is passed to device epitaxial structure growth andwafer fabrication.

FIG. 2A shows a preferred process flow of making ELP wafer substrateincorporating layer transfer in cross sectional diagrams. It starts withan assembly substrate 240 (Inset 1) which preferably can be etched toinclude a pattern with any desired etch profile including throughsubstrate vias 245 (Inset 2). The entire etched assembly substrate withthrough substrate vias can be coated preferably with one or moreinterfacial layers 248 (Inset 3) by appropriate techniques such as thinfilm deposition or coating, oxidation, nitridation, etc. The purpose ofthe interfacial layer(s) 248 is twofold: first to provide an inertsurface void of defects and crystal grains in through substrate vias 245so that the surface does not impede epitaxial crystal growth within thethrough substrate vias 245; and second to provide better Coefficient ofThermal Expansion (CTE) match between the assembly substrate 240 andepitaxial islands 250 and 251 to be grown. The specific composition,thickness, etc. of the interfacial layers 248 can be selected based onroutine testing and optimization.

One or more crystalline substrates 220 and 221 (Inset 4) may be usedpreferably to provide templates for homoepitaxy island growth. Thecrystalline substrates 220 and 221 (Inset 4) can be combined with etchedand coated assembly substrate 249 (Insets 3 and 8) where crystallinesubstrates are not atomic bonded to the etched and coated assemblysubstrate but are preferably mechanically pressed or held in physicalcontact using any conventional means against each other (Inset 8).

For ELP epitaxial island/pillar growth of two or more differentcrystalline materials, selective masking enables epitaxial island/pillargrowth of one material at a time. Thus in Inset 9, a masking layer 255is applied to cover through substrate via 245 over the crystallinesubstrate(s) 221. The masking layer 255 preferably can be photoresist oranother material that can be made as a mask and is easily removable.With the vias covered over crystalline(s) 221, epitaxial islands 250 canbe grown over crystalline(s) 220 (Inset 10). After the completion ofepitaxial islands/pillars 250, the masking layer 255 can be removed(Inset 11).

To prepare epitaxial island/pillar growth over crystalline substrate(s)221, preferably a masking layer 255 can be applied over grown epitaxialislands/pillars 250 (Inset 12). The masking layer 255 can be over theetched and coated assembly substrate 249 and previously formed epitaxialislands/pillars. Once the first grown epitaxial islands/pillars 250 aremasked or protected, a group of second epitaxial islands/pillars 251 canbe grown over crystalline substrate(s) 221 (Inset 13).

After the completion of epitaxial islands 251, masking layer 255 can beremoved (Inset 14). Crystalline substrates 220 and 221 may be thinneddown or completely removed to form an ELP substrate 260 (Inset 22).

As shown in Inset 5, as an alternative, layer transfer may be performedon crystalline substrates 220 and 221 before epitaxial island growth. Anexfoliation plane 222 preferably can be created within the crystallinesubstrates 220, 221 by any suitable layer transfer technique such as ionimplantation as discussed above (Inset 5). Handling substrates 230 arepreferably bonded to a top surface of transferring layer (Inset 6) usingany number of known techniques. By annealing or other appropriatetechniques to initiate layer exfoliation along the exfoliation plane222, transferred layers 225 are left bonded to handling substrates 230(Inset 7). Insets 15 to 21 correspond to the same process sequence asdescribed in Insets 8 to 14. At the completion of epitaxial islandgrowth 250 and 251 (Inset 21), the handling substrates 230 preferablycan be removed from the transferred layer 225 to form the ELP substrate260 (Inset 22).

FIG. 2B is an illustration of an alternative process flow using ELPwafer substrate for heterogeneous integration incorporating layertransfer after epitaxial island growth. Inset 23 in FIG. 2B correspondsto Inset 22 in FIG. 2A. The ELP substrate 260 consists of etched andcoated assembly substrate 249, thinned or layer transferred crystallinelayer 225, and grown epitaxial islands 250 and 251 made of one or morematerials. The crystalline layer 225 may be completely removed. Forheterogeneous integration of devices built on epitaxial islands 250 and251 and devices built on the material of assembly substrate 240, thecoated layer 248 preferably may be removed to leave an uncoated surface254 (Inset 24) for further device fabrication and circuit integration.

From the perspectives of material, processing, and assembly, ELP makesefficient use of compound semiconductor material by growing islands orpillars which can be interconnected—rather than wafers—and has theability to integrate several different materials on the same assemblysubstrate platform (e.g. silicon) using existing wafer fabricationprocesses. Wafer level heterogeneous integration is readily achievableby selective masking and demasking of ELP islands and assembly substratearea by either fabricating each microsystem sequentially or fabricatingmultiple microsystems by inserting modular steps of one microsystem intothe flow of another microsystem at appropriate steps while preservingthe electrical integrity of all microsystems.

In FIG. 2B, the sequence of fabricating microsystems serves as anillustration only and can be changed depending on critical processparameters among the microsystems. A straightforward heterogeneousprocess integration approach is to first preferably fabricate keystep(s) requiring high temperature followed by building individualmicrosystems by masking or unmasking ELP islands, and finishing bydeposition of interconnects (e.g. copper and/or carbon nanotube) betweenmicrosystems. Other considerations may include photolithographicresolution, layer step coverage, etch stop control, and so on in athree-dimensional (3D) circuit topology.

Herein, the sequence begins with fabricating devices and a microsystembuilt on the material of an assembly substrate first and then later onepitaxial islands/pillars. In Inset 25, a masking layer 255 ispreferably coated on the surface of epitaxial islands 250 and 251.Microsystem 270 is then preferably grown in a selected pattern based onmask 255 and consists of an electrical network of active devices,passive elements as resistors, inductors, and capacitors, transmissionlines, voltage and current sources, switches, resonators, etc. that arefabricated on assembly substrate material 240 (Inset 26).

By removing masking layer 255 from the surface of epitaxialislands/pillars 250 and 251 (Inset 27), additional microsystems 280 canbe fabricated on the epitaxial islands 250 and 251 (Inset 28).Interconnects (with or without final passivation) 290 are formed topreferably connect microsystems 270 and 280 (Inset 29) to completeheterogeneous integration. The thin bottom crystalline layer 225 may beremoved and planarized at the end of fabrication (Inset 30).

As used herein a “microsystem” refers to a combination of differentmicrodevices made from or on a single semiconductor material. Forexample, microsystem 270 can represent a collection of siliconintegrated circuits and microsystem 280 can represent devices made fromor on one or more compound semiconductors. For example, one could be aGaAs-based radio frequency integrated circuits and another could beGaN-based radio frequency integrated circuits or optical waveguidecouplers, or InP-based photonic circuits, etc.

As an alternative a layer transfer as described in FIG. 1B may beperformed on the ELP substrate 260 preferably creating a uniformexfoliation plane 222 (Inset 31) within the assembly substrate andepitaxial islands. A handling substrate 230 is preferably bonded to thetop surface of transferring layer 225. Annealing or other applicabletechniques is preferably applied to initiate exfoliation along theexfoliation plane 222. Insets 33 to 38 follow the same descriptions asInsets 24 to 29, to create two separate but interconnected microsystems.At the completion of heterogeneous integration, the handling substrate230 may be removed (Inset 39).

It will be apparent to those skilled in the art that the above is notintended to be an exhaustive description of every embodiment which canbe rendered in accordance with the present teachings. Other embodimentscould be constructed which use a combination of features from the abovedescribed exemplary forms. Accordingly the present disclosure will beunderstood by skilled artisans to describe and enable a number of suchvariants as well

What is claimed is:
 1. A method of forming an epitaxial structurecomprising: mounting a patterned epitaxial structure contained within anassembly substrate to a separate crystalline substrate; implanting anion species suitable for exfoliation into said assembly substrate toform an ion implanted exfoliation layer in said assembly substrate;bonding a handling substrate to said assembly substrate; separating saidhandling substrate and ion implanted exfoliation layer from saidassembly substrate; wherein at least a first portion of said assemblysubstrate with said patterned epitaxial structure remains bonded to saidhandling substrate.
 2. The method of claim 1 further including a step:forming said patterned epitaxial structure within said assemblysubstrate.
 3. The method of claim 1 wherein a second portion of saidassembly substrate remains bonded to said crystalline substrate.
 4. Themethod of claim 2 further including a step: performing an additionalexfoliation process on said second portion of said assembly substrateand said crystalline substrate to form a second exfoliation layer withinsaid assembly substrate.
 5. The method of claim 1 wherein a firstmicrosystem comprised of a first material is formed on a first region ofsaid first portion of said assembly substrate, and a separate secondmicrosystem comprised of a second material is formed on a secondseparate region of said first portion of said assembly substrate.
 6. Themethod of claim 5 wherein said first material is silicon basedsemiconductor, and said second material is one or more compoundsemiconductors.
 7. The method of claim 4 wherein additional processingcan be done to form devices on said second portion of said assemblysubstrate.
 8. A method of forming an epitaxial structure comprising:implanting an ion species suitable for exfoliation into a crystallinesubstrate to form an ion implanted region in said crystalline substrate;mounting an assembly substrate over said ion implanted region; whereinsaid assembly substrate includes a number of apertures extending therethrough forming an assembly pattern; growing an epitaxial materialwithin said assembly pattern to form an epitaxial pattern; whereinduring growing of said epitaxial material said ion implanted region isconverted to an ion induced exfoliation region; further wherein duringsaid growing step said epitaxial pattern is also separated from saidcrystalline substrate.
 9. The method of claim 8 wherein said ion speciesis selected such that an annealing process to induce exfoliation occursat approximately a same temperature as said epitaxial growing step. 10.An epitaxial structure comprising: a solid assembly substrate containinga patterned epitaxial structure extending from a top surface to a bottomsurface of said assembly substrate; an ion implanted exfoliated layercontained within a first plane extending laterally through said assemblysubstrate parallel to at least said top surface or bottom surface;wherein said solid assembly substrate is adapted to be divided into twoseparate composite halves along said first plane, such that each of saidtwo separate composite halves contains a separate epitaxial patterncapable of forming electronic and/or other microdevices.
 11. Theepitaxial structure of claim 10 further including a separate crystallinesubstrate attached to said bottom surface of said assembly substrate.12. The epitaxial structure of claim 10 further including a separatehandling substrate bonded to said top surface of said assemblysubstrate.
 13. An epitaxial structure situated in an assembly substratecomprising: a first epitaxial circuit in the assembly substratecomprising first electronic and/or other microdevices made of a firstepitaxial material situated in a first surface region of the epitaxialstructure; a second epitaxial circuit in the assembly substratecomprising second electronic devices made of a second epitaxial materialsituated in a second surface region of the epitaxial structure; whereinsaid second epitaxial material is different from said first epitaxialmaterial; further wherein said first surface region is adjacent to atleast portions of said second surface region; an interconnect structurefor coupling said first electronic devices and second electronicdevices.
 14. The epitaxial structure of claim 13 further including aninterface layer situated between the first and second epitaxialmaterials and the assembly substrate.
 15. The epitaxial structure ofclaim 13 further including an exfoliation layer situated within theassembly substrate and said first and second epitaxial materials.